Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device

ABSTRACT

Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.

BACKGROUND

1. Technical Field

This invention relates generally to the field of semiconductors, andmore particularly, to forming a nitride spacer to protect a FinFETdevice.

2. Related Art

A typical integrated circuit (IC) chip includes a stack of severallevels or sequentially formed layers of shapes. Each layer is stacked oroverlaid on a prior layer and patterned to form the shapes that definedevices (e.g., field effect transistors (FETs)) and connect the devicesinto circuits. In a typical state of the art complementary insulatedgate FET process, such as what is normally referred to as CMOS, layersare formed on a wafer to form the devices on a surface of the wafer.Further, the surface may be the surface of a silicon layer on a siliconon insulator (SOI) wafer. A simple FET is formed by the intersection oftwo shapes, a gate layer rectangle on a silicon island formed from thesilicon surface layer. Each of these layers of shapes, also known asmask levels or layers, may be created or printed optically throughwell-known photolithographic masking, developing, and level definition(e.g., etching, implanting, deposition, etc.).

The FinFET is a transistor design that attempts to overcome the issuesof short-channel effect encountered by deep submicron transistors, suchas drain-induced barrier lowering (DIBL). Such effects make it harderfor the voltage on a gate electrode to deplete the channel underneathand stop the flow of carriers through the channel—in other words, toturn the transistor off. By raising the channel above the surface of thewafer instead of creating the channel just below the surface, it ispossible to wrap the gate around all but one of its sides, providingmuch greater electrostatic control over the carriers within it.

While FinFET technology can provide superior levels of scalability, newchallenges can arise in designing and/or fabricating these devices. Forexample, processes used to remove materials during the fabricationprocess can have unintended effects on other components of the device.These effects can be exacerbated by the unique shapes that thesecomponents may assume in the FinFET model.

SUMMARY

In general, approaches for forming an oxide cap to protect asemiconductor device (e.g., a fin field effect transistor device(FinFET)) are provided. Specifically, approaches are provided forforming an oxide cap over a subset (e.g., SiP regions) of raised sourcedrain (RSD) structures on the set of fins of the FinFET device tomitigate damage during subsequent processing. The oxide spacer isdeposited before the removal of a nitride capping layer from the FinFETdevice (e.g., by a hot phosphorus wash). The oxide cap on top of the RSDstructures will be preserved throughout the removal of the nitridecapping layer to provide hardmask protection during this process.

One aspect of the present invention includes a method for forming adevice, the method comprising: forming a set of gate structures over afinned substrate, each of the set of gate structures comprising anitride capping layer; forming a set of raised source drain (RSD)structures on the finned substrate; forming an oxide cap over a subsetof the RSD structures; and removing the nitride capping layer.

Another aspect of the present invention includes a method for forming anoxide cap to protect a fin-shaped field effect transistor (FinFET)device, the method comprising: forming a set of gate structures over afinned substrate, each of the set of gate structures comprising anitride capping layer; forming a set of raised source drain (RSD)structures on the finned substrate; forming a silicate over a subset ofthe RSD structures; oxidizing the silicate to form the oxide cap; andremoving the nitride capping layer.

Yet another aspect of the present invention includes a fin-shaped fieldeffect transistor (FinFET) device, formed via a process, comprising:forming a set of fins from a substrate to get a finned substrate;forming a set of gate structures over the finned substrate, each of theset of gate structures comprising a nitride capping layer; growing a setof epitaxial phosphorus-doped Si (SiP) regions over a subset of the setof gate structures; growing a silicate on the SiP regions; oxidizing thesilicate using a plasma oxidation process to form an oxide cap; removingthe nitride capping layer via a hot phosphorus rinse, wherein the oxidecap prevents damage to the SiP regions from the hot phosphorus rinse;and removing the oxide cap from the SiP regions.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings in which:

FIG. 1 shows a FinFET semiconductor device according to an embodiment ofthe present invention;

FIG. 2 shows a “dummy” gate formation according to an embodiment of thepresent invention;

FIG. 3 shows a spacer formation according to an embodiment of thepresent invention;

FIG. 4 shows a nitride cap formation according to an embodiment of thepresent invention;

FIG. 5 shows a formation of raise source drain (RSD) structuresaccording to an embodiment of the present invention;

FIG. 6 shows RSD structures having SiP and SiGe regions according to anembodiment of the present invention;

FIG. 7 shows a formation of a silicate on the SiP regions according toan embodiment of the present invention;

FIG. 8 shows an oxidizing of the silicate to form an oxide cap accordingto an embodiment of the present invention; and

FIG. 9 shows a removal of a nitride capping layer according anembodiment of the present invention.

The drawings are not necessarily to scale. The drawings are merelyrepresentations, not intended to portray specific parameters of theinvention. The drawings are intended to depict only typical embodimentsof the invention, and therefore should not be considered as limiting inscope. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Exemplary embodiments will now be described more fully herein withreference to the accompanying drawings, in which exemplary embodimentsare shown. It will be appreciated that this disclosure may be embodiedin many different forms and should not be construed as limited to theexemplary embodiments set forth herein. Rather, these exemplaryembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the scope of this disclosure to thoseskilled in the art.

As mentioned above, disclosed herein are approaches for forming an oxidecap to protect a semiconductor device (e.g., a fin field effecttransistor device (FinFET)). Specifically, approaches are provided forforming an oxide cap over a subset (e.g., SiP regions) of raised sourcedrain (RSD) structures on the set of fins of the FinFET device tomitigate damage during subsequent processing. The oxide spacer isdeposited before the removal of a nitride capping layer from the FinFETdevice (e.g., by a hot phosphorus wash). The oxide cap on top of the RSDstructures will be preserved throughout the removal of the nitridecapping layer to provide hardmask protection during this process.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of this disclosure.For example, as used herein, the singular forms “a”, “an”, and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. Furthermore, the use of the terms “a”, “an”, etc.,do not denote a limitation of quantity, but rather denote the presenceof at least one of the referenced items. It will be further understoodthat the terms “comprises” and/or “comprising”, or “includes” and/or“including”, when used in this specification, specify the presence ofstated features, regions, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, regions, integers, steps, operations, elements,components, and/or groups thereof.

Reference throughout this specification to “one embodiment,” “anembodiment,” “embodiments,” “exemplary embodiments,” or similar languagemeans that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the present invention. Thus, appearances of the phrases “in oneembodiment,” “in an embodiment,” “in embodiments” and similar languagethroughout this specification may, but do not necessarily, all refer tothe same embodiment.

The terms “overlying” or “atop”, “positioned on” or “positioned atop”,“underlying”, “beneath” or “below” mean that a first element, such as afirst structure, e.g., a first layer, is present on a second element,such as a second structure, e.g. a second layer, wherein interveningelements, such as an interface structure, e.g. interface layer, may bepresent between the first element and the second element.

As used herein, “depositing” may include any now known or laterdeveloped techniques appropriate for the material to be depositedincluding but not limited to, for example: chemical vapor deposition(CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapidthermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactionprocessing CVD (LRPCVD), metal-organic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, thermal oxidation, thermal nitridation, spin-onmethods, physical vapor deposition (PVD), atomic layer deposition (ALD),chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

Referring now to FIG. 1, an initial formation stage of a semiconductordevice 10 is shown. As depicted, the device 10 can be formed on asubstrate 12 by forming a set of fins 14 from the substrate. To thisextent, device 10 generally comprises a uniform, oxide-fin surfacehaving a fin region 14 and an oxide fill 16. In general, the oxide-finsurface is formed by polishing (e.g., via CMP) oxide fill 16 to a topsurface of fin region 14. This results in a substantially “planar” or“uniform” surface. In FIG. 2, a dummy gate 20 formation process iscommenced. Specifically, a gate material 22 and a hard mask layer 24 arepositioned on the surface (collectively referred to as a gate structureor “dummy” gate 20). In FIG. 3, a set of spacers 26 are added toopposing sides of the gate structure.

The term “substrate” 12 as used herein is intended to include asemiconductor substrate, a semiconductor epitaxial layer deposited orotherwise formed on a semiconductor substrate and/or any other type ofsemiconductor body, and all such structures are contemplated as fallingwithin the scope of the present invention. For example, thesemiconductor substrate 12 may comprise a semiconductor wafer (e.g.,silicon, SiGe, or an SOI wafer) or one or more die on a wafer, and anyepitaxial layers or other type semiconductor layers formed thereover orassociated therewith. A portion or entire semiconductor substrate 12 maybe amorphous, polycrystalline, or single-crystalline. In addition to theaforementioned types of semiconductor substrates, the semiconductorsubstrate 12 employed in the present invention may also comprise ahybrid oriented (HOT) semiconductor substrate in which the HOT substratehas surface regions of different crystallographic orientation. Thesemiconductor substrate 12 may be doped, undoped or contain dopedregions and undoped regions therein. The semiconductor substrate 12 maycontain regions with strain and regions without strain therein, orcontain regions of tensile strain and compressive strain.

Gate structures 20 may be fabricated using any suitable processincluding one or more photolithography and etch processes. Thephotolithography process may include forming a photoresist layer (notshown) overlying substrate 12 (e.g., on a silicon layer), exposing theresist to a pattern, performing post-exposure bake processes, anddeveloping the resist to form a masking element including the resist.The masking element may then be used to etch each gate 20 into thesilicon layer, e.g., using reactive ion etch (RIE) and/or other suitableprocesses.

In one embodiment, gate structures 20 are formed by a double-patterninglithography (DPL) process. DPL is a method of constructing a pattern ona substrate by dividing the pattern into two interleaved patterns. DPLallows enhanced feature (e.g., fin) density. In this embodiment, gatestructures 20 each include a gate electrode. Numerous other layers mayalso be present, for example, a gate dielectric layer, interface layers,and/or other suitable features. The gate dielectric layer may includedielectric material such as, silicon oxide, silicon nitride, siliconoxinitride, dielectric with a high dielectric constant (high k), and/orcombinations thereof. Examples of high k materials include hafniumsilicate, hafnium oxide, zirconium oxide, aluminum oxide, hafniumdioxide-alumina (HfO₂—Al₂O₃) alloy, and/or combinations thereof. Thegate dielectric layer may be formed using processes such as,photolithography patterning, oxidation, deposition, etching, and/orother suitable processes. The gate electrode may include polysilicon,silicon-germanium, a metal including metal compounds such as, Mo, Cu, W,Ti, Ta, TiN, TaN, NiSi, CoSi, and/or other suitable conductive materialsknown in the art. The gate electrode may be formed using processes suchas, physical vapor deposition (PVD), CVD, plasma-enhanced chemical vapordeposition (PECVD), atmospheric pressure chemical vapor deposition(APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD),atomic layer CVD (ALCVD), and/or other suitable processes which may befollowed, for example, by photolithography and/or etching processes.

Referring now to FIG. 4, device 10 further comprises a nitride cap(e.g., SiN) 28 formed over gate region 20. In one embodiment, nitridecap 28 can be formed from silicon by thermal or plasma conversion ofsilicon into nitride, i.e., by thermal nitridation or by plasmanitridation of silicon. Alternately, nitride cap 28 can be formed bydeposition of silicon nitride, for example, by chemical vapor deposition(CVD), or by plasma oxidation.

Referring now to FIG. 5, a formation of raised source drain (RSD)structures 30 according to an embodiment of the present invention isshown. As illustrated, an RSD structure 30 can be formed on each fin 14of FinFET device 10. RSD structure 30 can be grown as an epitaxialstructure or can be formed in any way now known or later developed.Further, RSD structure 30 can be formed using any material now known norlater developed for use as a source and/or drain.

Referring now to FIG. 6, FinFET device 10 having a set of RSD structures30 is shown. As illustrated, a subset of the fins 14 have been formedinto a set of NFET regions 32. Similarly, a subset of the fins 14 (e.g.,a remainder of some or all fins that were not formed into the set ofNFET regions 32) have been formed a set of PFET regions 34. A set ofphosphorus-doped Si (SiP) regions 36 of RSD structures 30 has beenformed in NFET regions 32. Similarly, a set of silicon germanium (SiGe)regions 38 of RSD structures 30 have been formed in PFET region 34.

It is often the case that, subsequent to the formation of RSD structures30, nitride capping layer 28 must be removed. This removal is oftenaccomplished with a hot phosphorus wash. However, the inventors of thepresent invention have discovered that current solutions for removingthe nitride capping layer 28 have certain disadvantages. For example, asshown in FIG. 6, nitride capping layer 28 and/or spacers 26 may havecertain irregularities, such as elevated region 40. Such irregularitiescan lead to portions of nitride capping layer 28 and/or spacers 26 beingremoved prior to other portions, leading to bleed-through of thesubstance (e.g., hot phosphorus wash) used to perform the removal. Thisbleed-through can cause damage to certain of RSD structures 30, inparticular SiP regions.

In order to reduce and/or substantially eliminate damage to the SiPregions 36 during the removal of the nitride capping layer 28, in thepresent invention, an oxide cap can be formed over a subset of RSDstructures 30 (e.g., SiP regions 36). For example, as shown in FIG. 7, asilicate 42 can be grown on SiP regions 36, e.g., using an epitaxialmethod, or the like. Note that silicate 42 that is grown on SiP regions36 is not present on SiGe regions 38 due to the fact that the SiGeregions 38 are covered with nitride capping layer 28. In any case,silicate 42 can be oxidized to form oxide cap 44. For example, thisoxidizing can include a thermal oxidation process with conventionalfurnace oxide process, an in situ steam generation (ISSG) or other rapidthermal oxidation technique, a plasma oxidation process and/or any otherprocess that is now known or later developed for oxidizing a Sideposition (e.g., converting silicon (S) to silicon oxide SiO2).

When, as shown in FIG. 9, nitride capping layer 28 and/or spacers 26 areremoved (e.g., using a hot phosphorus wash), oxide cap 44 will protectthe RSD structures 30 (e.g., SiP regions 36) upon which the oxide cap 44was formed. Oxide cap 44 can then be removed from the RSD structures 30and subsequent formation (e.g., of gates, contacts, etc.) can beresumed.

In various embodiments, design tools can be provided and configured tocreate the datasets used to pattern the semiconductor layers asdescribed herein. For example data sets can be created to generatephotomasks used during lithography operations to pattern the layers forstructures as described herein, including a set of gate structuresformed over a fined substrate, each of the set of gate structurescomprising a nitride capping layer, RSD structures formed on the finnedsubstrate, and an oxide cap formed over a subset of the RSD structures.Such design tools can include a collection of one or more modules andcan also be comprised of hardware, software or a combination thereof.Thus, for example, a tool can be a collection of one or more softwaremodules, hardware modules, software/hardware modules or any combinationor permutation thereof. As another example, a tool can be a computingdevice or other appliance on which software runs or in which hardware isimplemented. As used herein, a module might be implemented utilizing anyform of hardware, software, or a combination thereof. For example, oneor more processors, controllers, ASICs, PLAs, logical components,software routines or other mechanisms might be implemented to make up amodule. In implementation, the various modules described herein might beimplemented as discrete modules or the functions and features describedcan be shared in part or in total among one or more modules. In otherwords, as would be apparent to one of ordinary skill in the art afterreading this description, the various features and functionalitydescribed herein may be implemented in any given application and can beimplemented in one or more separate or shared modules in variouscombinations and permutations. Even though various features or elementsof functionality may be individually described or claimed as separatemodules, one of ordinary skill in the art will understand that thesefeatures and functionality can be shared among one or more commonsoftware and hardware elements, and such description shall not requireor imply that separate hardware or software components are used toimplement such features or functionality.

It is apparent that there has been provided methods for forming an oxidecap to protect a FinFET device. While the invention has beenparticularly shown and described in conjunction with exemplaryembodiments, it will be appreciated that variations and modificationswill occur to those skilled in the art. For example, although theillustrative embodiments are described herein as a series of acts orevents, it will be appreciated that the present invention is not limitedby the illustrated ordering of such acts or events unless specificallystated. Some acts may occur in different orders and/or concurrently withother acts or events apart from those illustrated and/or describedherein, in accordance with the invention. In addition, not allillustrated steps may be required to implement a methodology inaccordance with the present invention. Furthermore, the methodsaccording to the present invention may be implemented in associationwith the formation and/or processing of structures illustrated anddescribed herein as well as in association with other structures notillustrated. Therefore, it is to be understood that the appended claimsare intended to cover all such modifications and changes that fallwithin the true spirit of the invention.

What is claimed is: 1.-17. (canceled)
 18. A fin-shaped field effecttransistor (FinFET) device, formed via a process, comprising: forming aset of fins from a substrate to form a finned substrate; forming a setof gate structures over the finned substrate, each of the set of gatestructures comprising a nitride capping layer; growing a set ofepitaxial phosphorus-doped Si (SiP) regions over a subset of the set offins; growing a silicate on the SiP regions; oxidizing the silicateusing a plasma oxidation process to form an oxide cap; removing thenitride capping layer via a hot phosphorus rinse, wherein the oxide capprevents damage to the SiP regions from the hot phosphorus rinse; andremoving the oxide cap from the SiP regions.
 19. The FinFET deviceaccording to claim 18, the process further comprising: forming an NFETregion from a subset of the set of fins, wherein the SiP regions aregrown in the NFET region; forming a PFET region from a remainder of theset of fins; and growing a set of epitaxial silicon germanium (SiGe)regions of the RSD in the PFET region, wherein the oxide cap is notformed over the SiGe regions.
 20. The FinFET device according to claim19: wherein the silicate is grown on the SiP regions using an epitaxialprocess; and wherein the plasma oxidation process includes a thermaloxidation process.
 21. A fin-shaped field effect transistor (FinFET)device, formed via a process, comprising: forming a set of fins from asubstrate to form a finned substrate; forming a set of gate structuresover the finned substrate, each of the set of gate structures comprisinga nitride capping layer; forming a set of raised source drain (RSD)structures on the finned substrate, wherein a first subset of the RSDstructures includes an NFET region and a second subset of the RSDstructures includes a PFET region; forming an oxide cap over only thefirst subset of the RSD structures; and removing the nitride cappinglayer.
 22. The FinFET device according to claim 21, the process furthercomprising: forming a set of fins from the substrate to form the finnedsubstrate; and growing a RSD structure of the set on RSD structures oneach fin of the set of fins.
 23. The FinFET device according to claim22, the process further comprising: forming an NFET region from a subsetof the set of fins; and forming a PFET region from a remainder of theset of fins.
 24. The FinFET device according to claim 23, the processfurther comprising: forming a set of phosphorus-doped Si (SiP) regionsof the RSD in the NFET region; and forming a set of silicon germanium(SiGe) regions of the RSD in the PFET region.
 25. A fin-shaped fieldeffect transistor (FinFET) device, comprising: a finned substrate,comprising a substrate and a set of fins formed from the substrate; aset of gate structures over the finned substrate; a set of raised sourcedrain (RSD) structures, a first subset of the set of RSD structurescomprising an NFET region and a second subset of the set of RSDstructures comprising a PFET region.
 26. The FinFET device of claim 25,wherein one of the RSD structures is formed on each fin of the set offins.
 27. The FinFET device of claim 25, wherein the first subset of theset of RSD structures comprises a set of phosphorous-doped silicon (SiP)regions.
 28. The FinFET device of claim 27, wherein the SiP regionscomprise epitaxial SiP.
 29. The FinFET device of claim 25, wherein thesecond subset of the set of RSD structures comprises a set of silicongermanium (SiGe) regions.
 30. The FinFET device of claim 29, wherein theSiGe regions comprise epitaxial SiGe.